"Evolution or Revolution of the Microprocessor Era needed?"
Moderator: Jürgen Becker
Room Veleiros

12:00-13:30 Lunch

13:30-14:30 T2A Session: New Architectures and Compilers
Chair: Jürgen Becker
Room Veleiros

T2A-1: “Power-Aware Branch Target Prediction Using a New BTB Architecture”
   Hadi Sadeghi, Hamid Sarbazi-Azad and Hamid R. Zarandi
T2A-2: “FSM-Controlled Architectures for Linear Invasion”
   Farhadur Arifin, Richard Membarth, Abdulazim Amouri, Frank Hannig and Jürgen Teich

13:30-14:30 T2B Session: CAD and Tools
Chair: David Atienza
Room Carijós

T2B-1: “Fast Thermal-Aware Floorplanning using White-Space Optimization”
   Sheldon Logan and Matthew Guthaus
T2B-2: “Investigating Runtime Task Mapping for NoC-based Multiprocessor SoCs”
   Ewerson Carvalho, Ney Calazans and Fernando Moraes

14:30-16:00 PhD Forum (3 min each poster)
Chair: Lisane Brisolara
Room Veleiros

T1-1: "MARTE based design flow for partially reconfigurable anti-collision radar detection system"
Imran Rafiq Quadri, Alexis Muller, Samy Meftali, Jean-Luc Dekeyser (Advisor)
INRIA Lille Nord Europe – LIFL,  France
T1-2: "Embedded System to Perform Motor Decode in a Neural Prosthetic Application"
Spencer Kellis, Richard Brown (Advisor)
University of Utah, USA
T1-3:"Performance Impact of QoSS (Quality of Security Service) Inclusion for NoC-Based Systems"
Martha Johanna Sepúlveda Flórez, Marius Strum (Advisor)
Sao Paulo University – USP, Brazil
T1-4: "Technology-Accurate Variability-Aware Performance Macromodels for On-Chip Communication Synthesis"
Petru B. Bacinschi, Manfred Glesner (Advisor)
Technische Universitat Darmstadt, Germany
T1-5: " The case for interpreted languages in sensor networks"
Leonardo Steinfeld, Luigi Carro (Advisor), Fernando Silveira (Co-advisor)
Universidad de la República, Uruguay
Universidade Federal do Rio Grande do Sul – UFRGS, Brazil
T1-6: "Complemental Testing - A Novel Approach for High Level Test Data Generation"
Alair Dias Júnior, Diógenes Cecílio da Silva Júnior (Advisor)
Universidade Federal de Minas Gerais – UFMG, Brazil
T1-7: "A Self-Adaptive Approach to Increase Reliability of Processors "
Monica Magalhães Pereira, Luigi Carro (Advisor)
Universidade Federal do Rio Grande do Sul – UFRGS, Brazil
T1-8: "Improving Accuracy in Power Estimation by Exploiting Multi-Model
Techniques"
Felipe Klein, Guido Araujo, Rodolfo Azevedo (Advisor)
State University of Campinas – UNICAMP, Brazil
T1-9: "Gate Sizing for Cell-Based Local Optimizations"
Caio Graco P. Alegretti, André I. Reis (Advisor), Renato P. Ribas (Co-Advisor)
Federal University of Rio Grande do Sul – UFRGS, Brazil
T1-10: "Power and Timing Optimization of Mesh-based Clock Distribution Architectures"
Gustavo Reis Wilke, Ricardo Reis (Advisor)
Federal University of Rio Grande do Sul – UFRGS, Brazil
T1-11: "Low-Power Operation of Integrated Circuits in the Presence of Process Variation"
Amlan Ghosh, Richard B. Brown (Advisor)
University of Utah, USA
T1-12: "Reducing Power Leakage and NBTI Effects by Using Automatic Generated Cells"
Adriel Ziesemer, Ricardo Reis (Advisor)
Federal University of Rio Grande do Sul – UFRGS, Brazil
T1-13: "Heuristics for Cells and I/O Pads Partitioning Targeting 3D VLSI
Circuits"
Sandro Sawicki, Marcelo Johann, Ricardo Reis (Advisor)
Federal University of Rio Grande do Sul – UFRGS, Brazil

16:00-17:30 T3A Session: Testing and Design for Test
Chair: Salvador Mir
Room Veleiros

T3A-1: “Structural Heuristics for SAT-based ATPG”
Daniel Tille, Stephan Eggersglüß, Hoang M. Le and Rolf Drechsler
T3A-2: “SyntHorus: Highly Efficient Automatic Synthesis from PSL to HDL”
Yann Oddos, Katell Morin-Allory and Dominique Borrione

16:00-17:30 T3B Session: Physical Design, Low Power Design
Chair: Franz Rammig
Room Carijós

T3B-1: “On-Chip Timing Slack Monitoring”
Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine and Nadine Azemard
T3B-2:  “Energy Efficiency of SISO Algorithms for Turbo-Decoding Message-Passing LDPC Decoders”
Erick Amador, Vincent Rezard and Renaud Pacalet
T3B-3: ”Clocked and Asynchronous FIFO Characterization and Comparison”
Ho Suk Han and Kenneth Stevens

Wednesday, October 14, 2009

08:00-09:00 Registration

09:00-10:00 Keynote Talk:

"Emerging technologies and nanoscale computing fabrics"
                        Prof. Ian O'Connor - INL-ECL, Lyon, France (abstract)
Chair: Manfred Glesner
Room Veleiros

10:00-10:30 Coffee Break

10:30-12:00 W1A Session: Networks On Chip
Chair: Norbert Wehn
Room Veleiros

W1A-1: “Multipath Routing in TDM NoCs”
Radu Stefan and Kees Goossens
W1A-2: “Crosstalk fault tolerant NoC – design and evaluation”
Alzemiro Lucas and Fernando Moraes
W1A-3: “A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures”
Petru B. Bacinschi and Manfred Glesner

10:30-12:00 W1B Session: MPSoCs
Chair: Flavio Rech Wagner
Room Carijós

W1B-1: “Performance and Energy Evaluation of Memory Hierarchies in NoC-based MPSoCs under Latency”
Gustavo Girão, Daniel Barcelos and Flávio Rech Wagner
W1B-2: “Managing QoS Flows at Task Level in NoC-Based MPSoCs”
Everton Carara, Ney Calazans and Fernando Moraes
W1B-3: “Optimal Multi-Processor SoC Thermal Simulation via Adaptive Differential Equation Solvers”
Francesco Zanini, David Atienza, Ayse Kivilcim Coskun and Giovanni De Micheli

12:00-13:30 Lunch

13:30-14:30 W2A Session: Prototyping, Validation, Verification
Chair: P. A. Subrahmanyam
Room Veleiros

W2A-1: “Support Vector Machine Coverage Driven Verification for Communication Cores”
Edgar Romero, Raul Acosta, Marius Strum and Jiang Chau Wang
W2A-2:  “Observability-based Coverage-directed Path Generation using Pseudo-Boolean Optimization”
José Costa and José Monteiro

13:30-14:30 W2B Session: Reconfigurable Systems
Chair: Carlos Lang Lisboa
Room Carijós

W2B-1: “GenerateRCS: A High-Level Design Tool for Generating Reconfigurable Computing Systems”
Diana Goehringer, Jan Luhmann and Juergen Becker
W2B-2: “Highly Efficient Reconfigurable Routers in Networks-on-Chip”
Debora Matos, Caroline Concatto, Luigi Carro, Altamiro Susin, Marcio Kreutz and Fernanda Kastensmidt

14:30 – 16:00 W1 Interactive Poster Session (2 min each poster)
Chair: Sergio Bampi
Room Veleiros

W1-1:  “IVM: An Interoperable Verification Methodology for Iterative and Incremental Digital System Design”
Bruno Prado, Edna Barros, Gabriela Clemente, Luciano Silva, Adelmário Junior and Rômulo Bruno
W1-2: “Macro-modeling of analog blocks for SystemC-AMS simulation: A chemical sensor case-study”
Fabio Cenni, Emmanuel Simeu and Salvador Mir
W1-3: “BIST for Strongly-Indicating Asynchronous Circuits”
Deepali Koppad and Aris Efthymiou
W1-4: “Introduction of a Zonal Search Strategy for SVC Inter-Layer Prediction Module”
Ronaldo Husemann, Valter Roesler and Altamiro Susin
W1-5: “BrownPepper: a SystemC-based Simulator for Performance Evaluation of Networks-on-Chip”
Jaison Bruch, Magnos Pizzoni and Cesar Zeferino
W1-6: “Architectural Exploration of Forward 4x4 Hadamard Transform Applied to H.264/AVC Video Compression Standard”
André Silva, João Altermann, Sérgio Almeida and Eduardo Costa
W1-7: “Design Approach for a Low Power Video Decoder”
Elmar Uwe Kurt Melcher, Henrique Nascimento Cunha, Maria de Lourdes Nascimento, Fabrício Gutemberg Lélis de Melo and Matheus Bezerra Estrela Rodrigues
W1-8: “ A Dynamic Reconfiguration Approach for Accelerating Highly Defective Processors”
Monica Pereira and Luigi Carro
W1-9: “Tradeoffs of FPGA design of floating-point transcendental functions”
Daniel M. Muñoz, Diego F. Sánchez, Carlos H. Llanos and Mauricio Ayala-Rincon
W1-10: “Efficient Hardware Design for the Upsampling in the H.264/SVC Scalable Video Coding Extension”
Thaísa Silva, Fabiane Rediess, Luciano Agostini, Altamiro Susin and Sergio Bampi